1. Field of the Invention
The present invention relates to a microcomputer. More particularly, the present invention relates to a microcomputer to be connected with external circuits including memories via an external bus.
2. Description of Related Art
In general, in a microcomputer which can be connected with external circuits such as a memory (ROM, RAM, and so on), a gate array and an exclusive use IC via an external bus, and outputs an address/data signal and control signals such as a read/write signal to the external circuits and receives the address/data signal from the external circuits, due to a constraint in the number of terminals of the microcomputer, an address signal and a data signal are assigned to the same terminal and inputted or outputted at this terminal in a time division manner (i.e., multiplex bus method). Hence, the address/data signal outputted from the microcomputer must be separated into an address signal and a data signal outside the microcomputer. To this end, an address latch enable signal which stays at "H" level during outputting of the address signal is supplied from the micro computer to an address latch circuit. The address latch circuit latches the address signal so that the address/data signal is separated into the address signal and the data signal.
In some exclusive use ICs used for a specified purpose which is externally attached by a user as an external circuit, to reduce the number of the terminals of the exclusive use IC, separation into the address signal and the data signal is performed within the exclusive use IC. In this case, the exclusive use IC includes an address latch circuit, and a multiplex bus for the address/data signal and a control signal bus for an address latch enable signal are connected to the address latch circuit. The address signal is latched by the address latch circuit so that the address/data signal is separated into the address signal and the data signal.
FIG. 1 is a block diagram showing a conventional microcomputer connected with external circuits with the multiplex bus method as above. The microcomputer is indicated at the numerical reference 1. The microcomputer 1 comprises a CPU 2 which receives a clock signal generated by a clock signal generating circuit 71, decodes a predetermined program and controls a peripheral device in accordance with the content of the program. The microcomputer 1 is also provided with a peripheral circuit 3 which includes circuits such as an internal memory (ROM, RAM, and so on), a timer and an A-D conversion circuit. A bus interface circuit 4 which connects an internal bus and an external bus is also disposed in the microcomputer 1. Among the CPU 2, the peripheral circuit 3 and the bus interface circuit 4, the data signal is transferred through an internal data bus 5, the address signal is transferred through an internal address bus 6, and a control signal is transferred through an internal control signal bus 7.
A ROM 15, a RAM 16 and an exclusive use IC 17 which includes an address latch circuit 18 is disposed outside of the microcomputer 1. The address/data signal outputted from the bus interface circuit 4 is supplied to an address latch circuit 13 through an external address/data bus 11 so that an address signal (A) alone is provided to the ROM 15 and the RAM 16 through the external address bus 14. The address/data signal is supplied directly to the exclusive use IC 17. In FIG. 1, the symbol AIC indicates the address signal which is separated by the address latch circuit 18.
The control signal includes an address latch enable signal ALE for controlling a timing of latching the address signal in the address latch circuit 13, a write signal #WR for controlling a timing of writing data and a read signal #RD for controlling a timing of reading data. `#` included in numerals indicate signals means that the signal is active when the signal's level is "L". The control signal is supplied to the bus interface circuit 4 through the internal control signal bus 7, further to the ROM 15, the RAM 16 and the exclusive use IC 17 through an external control signal bus 12.
FIG. 2 is a circuit diagram showing the essential part of the bus interface circuit shown in FIG. 1, and particularly, showing a portion related to outputting of the control signals. The bus interface circuit 4 includes output buffers 20, 21 and 22 and output terminals 23, 24 and 25 which are respectively connected to the output buffers 20, 21 and 22. An internal address latch enable signal ALEint, an internal read signal #RDint and an internal write signal #WRint are supplied to the bus interface circuit 4 through the internal control signal bus 7, and are outputted to external control signal bus 12 from the output terminals 23 24 and 25 through the output buffers 20, 21 and 22, respectively, as the address latch enable signal ALE, the read signal #RD and the write signal #WR.
The ROM 15 and the RAM 16 each include an address terminal and a data terminal. The address signal A separated by the address latch circuit 13 in response to the address latch enable signal ALE is supplied to each address terminal through the external address bus 14. In response to the read signal #RD or the write signal #WR, the data signal is transferred between the external address/data bus 11 and the data terminals. On the other hand, since the exclusive use IC 17 includes the address latch circuit 18, the address/data signal and the address latch enable signal ALE are supplied directly to the exclusive use IC 17 (the address latch circuit 18).
FIG. 3 is a timing chart showing signals of the external bus of FIG. 1. In FIG. 3, the symbol .o slashed. indicates a clock signal. The address/data signal is a signal in which address signals A0, A1, A2 . . . and data signals D0, D1, . . . alternately appear. The address latch enable signal ALE rises to "H" level when the address/data signal switches to the address signal. After a certain period of time from the rise of the address latch enable signal ALE, the read signal #RD or the write signal #WR which is in a low active state falls. This period of time is determined depending on an element such as a memory.
In the address latch circuit 13, the address/data signal supplied to an input terminal of the address latch circuit 13 during the "H" level period of the address latch enable signal ALE is supplied, as it is, to an output terminal of the address latch circuit, 13. During the "L" level period of the address latch enable signal ALE, the address latch circuit 13 holds its former state (i.e., the address latch circuit 13 is a D latch. ). Hence, the address signal A changes to the next address upon a rise of the address latch enable signal ALE.
On the other hand, the address latch circuit 18 of the exclusive use IC 17 latches the address/data signal which is supplied to its input terminal during the "H" level period of the address latch enable signal ALE. The address latch circuit 18 outputs its state upon a fall of the address/data signal to "L" level (i.e, the address latch circuit 18 is a D flip-flop.). Hence, the address signal AIC changes to the next address upon a fall of the address latch enable signal ALE.
Thus, determining an address fast and hence being desirable for high-speed memory access, a D latch is used as an address latch for a memory in many cases. Strongly resistant against a noise introduced through an external address/data bus and an address latch enable signal line from outside, a D flip-flop is used as an address latch for an exclusive use IC in many cases. This forces to use two different types of address latches together on the same bus, which in turn causes the address determining times to be different from each other in some cases.
Since circuits such as the ROM 15, the RAM 16 and the exclusive use IC 17 require a certain period of time for an internally provided address decode circuit to operate, it demands a longer time than a prescribed time period from determination of the address signals A and AIC which are to be decoded until the read signal #RD or the write signal #WR changes to "L" level. In FIG. 3, the symbol t(ALE-WR)H expresses a time period from a rise of the address latch enable signal ALE to a fall of the write signal #WR. The symbol t(ALE-WR)L expresses a time period from a fall of the address latch enable signal ALE to a fall of the write signal #WR. The former, which can be long correspondingly to the "H" level period of the address latch enable signal ALE, causes no particular problem. However, the latter which is basically or originally short, needs consideration when the frequency level of the clock signal is to be increased aiming at high-speed operations. In the case as above, in particular, where address latches having different structures are used together, it is not allowed to increase the clock frequency level since this t(ALE-WR)L period must last at least for a certain period of time. For this reason, it is impossible to increase the speed of the operations of the system as a whole. Although the timing of a fall of the write signal #WR can be delayed to deal with this, such contradicts the flexibility of the microcomputer. This is because a timing is determined with a major attention directed to the exclusive use IC although the exclusive use IC is connected only to a special purpose circuit and demands a different time from that of a RAM which is to be always connected. In addition, in this case, the frequency level of the clock signal must be lowered in order to permit the "L" level of the write signal #WR (or the read signal #RD) to appear for a certain time period. This directly contradicts high-speed operations attained by activating the address signal during the "H" level of the address latch enable signal ALE. Hence, this method has only a very limited success.